When I first had the thought to start this project, it was clear the biggest challenge to overcome was finding the CPU and I/O chips. These couldn't be easily simulated. As it happened, an eBay auction came up for a MK14 chipset just then (just the chips, nothing else), and a few bids later I had secured them.
Since these may or may not work, I also looked for a backup plan. A quick Google for obsolete semiconductor brokers gave a couple of leads and a few days later I had my chips. Amazing what's still out there really
With the key semiconductors on hand, all that remained was to complete a design that met my design goals and to translate that in to a PCB.
I could have choosen to make an exact copy of the original machine as far as current techology allows. That would mean new RAM and ROM devices, but keeping all the original TTL memory decode and keyboard/display scan circuitry. However, I had decided to have multiple system images in the system RAM and ROM and to have firmware programmable address decoding. I also wanted to keep the chip count as low as possible - ideally just a single chip in addition to the CPU, I/O, RAM and ROM.
These factors mean that the system glue should be implemented in a CPLD (complex programmable logic device). But which one?
My first thought was to use a MACH device - originally from AMD, now manufactued by Lattice Semiconductor. I had designed with these in the past, and they have a very simple (if basic) programming language called ABL. They work at 5V, which many newer devices do not, which was great; but they also only had a maximum of 44 pins in non-SMD packages, which was not so great. Adding together all the pins I would need to mop up the address decoding and keyboard/display scan pushed the pin count past 60.
Undeterred, I draw up my design in my Eagle CAD package using 2 devices to get the total pin count I needed. However I found when it came to the PCB layout that it made it hard to meet my target PCB size without increasing the layer count too much. I decided to look around for a better alternative before compromising on size/layer count.
A colleague recommended the Altera 7000 series.They go up to an 84 pin PLCC package which I could solder without any special SM tools, and they can be JTAG programmed for in-circuit reconfiguration. The only issue - no ABL support. This meant it looked like a good time to learn VHDL which they do support. One learning curve later I had my code.
As described in the design goals, I wanted to have multiple banks of RAM and ROM so that several programmes (occupying all/lots of RAM) could be loaded at the same time. Select the right bank, and the code would be instantly there. I also wanted total flexibility over the memory map in the limited 4K original space - choose RAM or ROM at a given address at will. This would let me be entirely compatible with the original memory map for ROM repeats, or to trade those for working RAM.
Here's how it works:
Note that each 4K system image uses 4K of ROM and 4K of RAM. Unmapped areas are simply lost. Whilst wasteful, it is extremely flexible and with 512K of memory to play with it's not a problem. Bank select of the ROM and RAM is done via a 16 position hex switch and a big/small memory mode jumper.
In big memory mode, the SC/MP gets as much memory as it can handle - 32K RAM and 32K ROM (less 256 bytes for the display and I/O). Bit of a software challenge to know what to fill that with, but I'll come back to that later ...
There are 14 "big" images in total. (14 big images * 32K)+(16 original images * 4K) = total memory of 512K.
The CAD package I use (Eagle) handles up to 16 layer boards. I tried hard to squeeze this design on to 2 layers as per the original MK14. With 19 address lines for the big memories and dense PLCC sockets in the design, this wasn't possible. I ended up with 3 signal layers and a groundplane for a 4 layer board.The great company I usually use for PCB manufacture (Olimex) only handle 2 layer boards. I'm therefore trying these guys who do good prices on 4 layer boards.